PROGRAMMING INFORMATION 2.1 DATA FORMATS The basic data format for the 2100 Computer is a 16-bit word. Bit positions are numbered from 0 to 15, in order of increas- ing significance. Bit position 15 of the data format is used for the sign bit; a "0" in this position indicates a positive number and a "1" indicates a negative number. The data is assumed to be a whole number, thus the binary point is assumed to be to the right of the number. The basic word, as shown in figure 2.1, can also be divided into two 8-bit bytes or combined to form a 32-bit doubleword. The byte format is used for character-oriented input/output devices. Packing of the two bytes into one word is accomplished by the software drivers. In I/O operations the higher order byte (Byte 1) is the first to be transferred. The integer doubleword format is used for extended precision arith- metic in conjunction with the ten extended arithmetic instructions. Bit 15 of the most significant word is the sign bit, and the binary point is assumed to be to the right of the least significant word. The floating point doubleword format is used with floating point software. Bit 15 of the most significant word is the mantissa sign bit and bit 0 of the least significant word is the exponent sign bit. Bits 1 through 7 are used to express the exponent, and the remain- ing bits (8 through 15 of the least significant word and 0 through 14 of the most significant word) are used to express the mantissa. The mantissa is assumed to be a fractional value, thus the binary points appears to the left of the mantissa. Software converts deci- mal numbers to this binary form and normalizes the quantity ex- pressed (sign and leading mantissa bit differ). If either the man- tissa or the exponent is negative, that part is stored in two's com- plement form. The number must be in the approximate range of 10**-38 through 10**38. 2-1 WORD FORMAT Least significant Sign bit data bit / / --------------------------------------------------------------- | | | | | | | | | | | | | | | | | --------------------------------------------------------------- . 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \ Binary point PACKED BYTE FORMAT --------- Byte 1 ---------- --------- Byte 2 ---------- / \ / \ --------------------------------------------------------------- | | | | | | | | | | | | | | | | | --------------------------------------------------------------- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTEGER DOUBLE WORD Sign bit / --------------------------------------------------------------- | | | | | | | | | | | | | | | | | --------------------------------------------------------------- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 --------------------------------------------------------------- | | | | | | | | | | | | | | | | | --------------------------------------------------------------- . 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \ Binary point FLOATING POINT DOUBLE WORD Sign bit / --------------------------------------------------------------- | | | | | | | | | | | | | | | | | ---.----------------------------------------------------------- 15 | 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | Binary Exponent Point sign \ --------------------------------------------------------------- | | | | | | | | | | | | | | | | | --------------------------------------------------------------- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |<--- Exponent (7 bits) --->| Figure 2.1. Data Formats and Octal Notation 2-2 Figure 2.1 also illustrates the octal notation of data for both single- length and double-length words. Each group of three bits, begin- ning at the right, is combined to form an octal digit. Each digit to the left increases in significance. A single-length 16-bit word can therefore be fully expressed by six octal digits and a double-length 32-bit word can be fully expressed by 11 octal digits. Octal nota- tion is not shown for byte or floating point formats, since bytes normally represent characters and floating point numbers are given in decimal form. For single-word data, the range of representable numbers is +32,767 to -32,768 (decimal) or +77,777 to -100,000 (octal). For doubleword integer data, the range is +2,147,483,647 to -2,147,483,648 (decimal), or +17,777,777,777 to -20,000,000,000 (octal). 2.2 MEMORY ADDRESSING The 2100A Computer can be equipped with any one of six mem- ory configurations, from 4K to 32K (K = 1024 words). The avail- able configurations, which determine the addressing range, are: 4K, 8K, 12K, 16K, 24K, 32K. 2.2.1 PAGING The computer memory is logically divided into pages of 1024 words each. A page is defined as the largest block of memory which can be directly addressed by the memory address bits of a memory reference instruction (single-length). These memory ref- erence instructions have 10 bits to specify a memory address, and thus the page size is 1024 locations (2000 in octal notation). Octal addresses for each page, up to the maximum memory size, are given in table 2.1. Provision is made to address directly one of two pages: page zero (the base page, consisting of locations 00000 through 01777), and the current page (the page in which the instruction itself is located.) Memory reference instructions include a bit (bit 10) reserved to specify one or the other of these two pages. To address locations 2-3 Memory Size Page Octal Addresses 0 00000 to 01777 1 02000 to 03777 2 04000 to 05777 4K 3 06000 to 07777 4 10000 to 11777 5 12000 to 13777 6 14000 to 15777 4K 7 16000 to 17777 8 20000 to 21777 9 22000 to 23777 10 24000 to 25777 12K 11 26000 to 27777 12 30000 to 31777 13 32000 to 33777 14 34000 to 35777 16K 15 36000 to 37777 16 40000 to 41777 17 42000 to 43777 18 44000 to 45777 19 46000 to 47777 20 50000 to 51777 21 52000 to 53777 22 54000 to 55777 24K 23 56000 to 57777 24 60000 to 61777 25 62000 to 63777 26 64000 to 65777 27 66000 to 67777 28 70000 to 71777 29 72000 to 73777 30 74000 to 75777 32K 31 76000 to 77777 Table 2.1. Memory Pages 2-4 in any other page, indirect addressing is used. Page references are specified by bit 10 as follows: Logic 0 = Page Zero (Z) Logic 1 = Current Page (C) 2.2.2 INDIRECT ADDRESSING All memory reference instructions reserve a bit to specify direct or indirect addressing. For single-length memory reference instruc- tions, bit 15 of the instruction word is used; for extended arith- metic memory reference instructions, bit 15 of the address word is used. Indirect addressing uses the address part of the instruction to access another word in memory, which is taken as a new memory reference for the same instruction. This new address word is a full 16 bits long, 15 bits of address plus another direct-indirect bit. The 15-bit length of the address permits access to any location in mem- ory. If bit 15 again specifies indirect addressing, still another ad- dress is obtained; this multiple-step indirect addressing may be done to any number of levels. The first address obtained in the indirect phase which does not specify another indirect level be- comes the effective address for the instruction. Direct or indirect addressing is specified by bit 15 as follows: Logic 0 = Direct Logic 1 = Indirect 2.2.3 RESERVED LOCATIONS The first 64 memory locations of the base page (octal addresses 00000 through 00077) are reserved as listed below. The first two addresses are the A and B flip-flop register addresses and are not considered as core storage locations. (The actual corresponding core locations can, however, be loaded and read via the operator panel.) Locations 4 through 77 are reserved in the sense that interrupt wiring is present for the priority order given. As long as the loca- tions do not have actual interrupt assignments (as determined by the input/output devices included in the user's system), these loca- tions may be used for program purposes. 2-5 00000 Address of A-register 00001 Address of B-register 00002 For exit sequence if A and B contents are used as 00003 executable words 00004 Interrupt location, highest priority (reserved for power fail interrupts) 00005 Reserved for memory parity and memory protect interrupts 00006 Reserved for direct memory access 00007 Reserved for direct memory access 00010 thru Interrupt locations in decreasing order of priority 00077 The last 64 locations of memory (any size) are reserved for the basic binary loader. The basic binary loader is a permanently resi- dent program to permit loading of binary information from punched paper tape (or disc, etc.) into memory. Unless specifically enabled by a panel switch, the loader locations are protected so they may not be altered or used in any way. 2.2.4 NONEXISTENT MEMORY Nonexistent memory is defined as those memory locations not physically implemented in the machine (up to the maximum of 32K) and the last 64 locations of implemented memory when not enabled from the front panel. Any attempt to write into non- existent memory will be ignored (no operation). Any attempt to read from a non-existent memory location will return an all-zero word; no parity error occurs. 2-6 2.3 HARDWARE REGISTERS THe 2100A Computer has six 16-bit working registers, two one- bit registers, and (on the operator panel) one 16-bit display regis- ter. The functions of these registers are described as follows: M-REGISTER. The M-register hold the address of the memory cell currently being read or written into. T-REGISTER (MEMORY DATA). All data transferred into or out of memory is routed through the memory data register. When dis- played, the display indicates the contents of the memory location currently pointed to by the M-register. The displayed data will go back into that location when any other action is taken (such as dis- playing some other register or beginning a run operation). P-REGISTER. The P-register holds the address of the next instruc- tion to be fetched out fo memory. Since this is a "look-ahead" register, the P-register value will frequently differ from the M- register value. Table 2.2 lists P- and M-register contents for each of five different computer states, assuming the computer is halted. A-REGISTER. The A-register is an accumulator, holding the results of arithmetic and logical operations performed by programmed instructions. This register may be addressed by any memory refer- ence instruction as location 00000, thus permitting inter-register operation such as "add B to A", "compare B with A," etc., using a single-word instruction. P-REGISTER M-REGISTER COMPUTER STATUS contains address of contains address of FETCH Current instruction Last memory access INDIRECT (after FETCH) Current instruction Current instruction INDIRECT (after INDIRECT) Current instruction Last memory access EXECUTE (after FETCH) Next instruction Current instruction EXECUTE (after INDIRECT) Next instruction Last memory access Table 2.2. P- and M-Register Indications 2-7 B-REGISTER. The B-register is a second accumulator, which can hold the results of arithmetic operations completely independent of the A-register. The B-register may be addressed by any memory reference instruction as location 00001 for inter-register operations with A. S-REGISTER. The switch (S) register is a 16-bit utility register. In the halt mode, it may be manually loaded via the display reg- ister. In the run mode it may be addressed as an I/O device (select code 01) and receive and read back data to and from the accumulators. EXTEND. The extend bit (E) is a one-bit register, and is used to link the A- and B-registers by rotate instructions or to indicate a carry from bit 15 of the A- or B-registers by an add instruction (ADA, ADB) or increment instruction (INA, INB, but not ISZ) for multiple-precision arithmetic. If already set, the extend bit is not complemented by a carry. It may be set, cleared, comple- mented, or tested by program instruction. The extend bit is set when the EXTEND light is on ("1") and clear when off ("0"). OVERFLOW. The overflow bit is a one-bit register which indicates that an add instruction (ADA, ADB), divide instruction (DIV), or an increment instruction (INA or INB, but not ISZ) referenc- ing the A- and B-registers has caused (or will cause)the accumu- lators to exceed the maximum positive or negative number which they can contain. By program instructions, the overflow bit may be cleared, set or tested. The OVF light remains on until the bit is cleared by an instruction and is not complemented if a second overflow occurs before being cleared. It will not be set by any shift or rotate instructions, except ASL (refer to definition in Section III). DISPLAY REGISTER. The display register is included on the standard operator panel. It provides a means of displaying and modifying the contents of any of the six 16-bit working registers when the computer is in the halt mode. Each pushbutton is illumi- nated to indicate a content of "1," and is non-illuminated to indi- cate a content of "0." Each time a pushbutton is pressed, the content changes state. When the computer is in the run mode, the display register permanently displays the S-register contents. 2-8 2.4 INSTRUCTION FORMATS Instructions for the 2100A Computer are classified according to format. The five formats used are illustrated in figure 2.2 and are described as follows. In all cases where a single bit is used to select one of two cases (e.g., D/I), the choice is made by coding a logic 0 or 1 respectively (i.e., 0/1). MEMORY REFERENCE. This class of instructions combines an instruction code and a memory address into one word. This type of instructions is therefore used to execute some function involving data in a specific memory location. Examples are storing, retriev- ing, and combining memory data to or from the accumulators, or causing the program to jump to the specified location. The cell referenced (i.e., the absolute address) is determined by a combination of the ten memory address bits in the instruction word (0 through 9) and five bits (10 through 14) assumed from the current condition of the P-register. This means that memory reference instructions can directly address any word in the current page; additionally, if the instruciton is given in some location other than the base page (page zero), bit 10 of the instruction word doubles the addressing range to 2048 words by allowing selection of either page zero or current page. (This causes bits 10 through 14 of the address in the M-register to be reset to zero, instead of assuming the current indication of the P-register.) This feature provides a convenient linkage between all pages of memory, since page zero can be reached directly from any other page. As discussed earlier, bit 15 is used to specify direct or indirect addressing. Also note that since the A- and B-registers can be ad- dressed, any single-word memory reference instruction can apply to either of these registers as well as to memory cells. For example, ADA 0001 means add the contents of the B-register (its address being 0001) to the A-register; specify page zero for these opera- tions, since the A- and B-register addresses are on page zero. REGISTER REFERENCE. These instructions, in general, manipu- late bits in the A-, B- and E-registers. There is no reference to memory. This type includes 39 basic instructions, which are com- binable to form a one-word multiple instruction that can operate in various ways on the contents of the A-, B- or E-registers. The 2-9 MEMORY REFERENCE --------------------------------------------------------------- | | | | | |D/I| Instruction |Z/C| Memory Address | | | | | | --------------------------------------------------------------- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REGISTER REFERENCE --------------------------------------------------------------- | | | | | | Class |A/B|S/A| Microinstructions | | | | | | --------------------------------------------------------------- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INPUT/OUTPUT --------------------------------------------------------------- | | | | | | Class |A/B| Instruction | Channel No. | | | | | | --------------------------------------------------------------- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTENDED ARITHMETIC MEMORY REFERENCE --------------------------------------------------------------- | | | | | | | Class | | | Instruction | (Zeroes) | | | | | | | --------------------------------------------------------------- --------------------------------------------------------------- | | | |D/I| Memory Address | | | | --------------------------------------------------------------- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTENDED ARITHMETIC REGISTER --------------------------------------------------------------- | | | | | | | Class | | | Instruction | No. of Shifts | | | | | | | --------------------------------------------------------------- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 2.2 Instruction Formats 2-10 39 instructions are divided into two subgroups, the shift-rotate group (SRG) and the alter-skip group (ASG). These subgroups are specified by bit 10. Typical operations are clear and/or com- plement a register, conditional skips, and register increment. INPUT/OUTPUT. The input/output class of instructions uses bits 6 through 11 for a variety of I/O instructions, and bits 0 through 5 to apply the instruction to a specific I/O channel. This provides a means of controlling all devices connected to the I/O channels, and for transferring data in or out. Also included in this group are instructions to control the interrupt system, overflow bit, and computer halt. EXTENDED ARITHMETIC MEMORY REFERENCE. Like the single-word memory reference instruction above, the complete in- structon includes an instruction code and a memory address. In this case, however, two words are required. The first word specifies the extended arithmetic class (bits 12 through 15 and 10) and the instruction code bits 4 through 9 and 11). Bits 0 thourgh 3 are not needed and are coded with zeros. The second word specifies the memory address of the operand. Since a full 15 bits are used for the address, this type of instruction may directly address any lo- cation in memory. As with all memory reference instructions, bit 15 may be used to specify indirect addressing. Operations pro- vided by this class of instructions are integer multiply and divide (using double-length product and dividend), and double load and double store. EXTENDED ARITHMETIC REGISTER REFERENCE. This class of instrucitons provides long shifts and rotates on the combined A- and B-registers. Bits 12 through 15 and 10 identify the extended arithmetic class, and bits 4 through 9 and 11 specify the direction and type of shift. Bits 0 through 3 are used to specify the number of shifts, which can range from 1 to 16 places. 2.5 INTERRUPT SYSTEM The computer interrupt system has 60 distinct interrupt levels. Each level has a unique priority assigned to it, and is associated with a numerically corresponding interrupt location in core memory. 2-11 As an example of the simplicity of this system: a service request from I/O channel 13 will cause an interrupt to core location 00013. The request for service will be granted on a priority basis higher than channel 14 but lower than channel 12. Thus a transfer in progress via channel 14 would be suspended to let channel 13 proceed, but a transfer via channel 12 could not be interrupted by channel 13. Under program control, any device may be selectively enabled or disabled, thus switching the device in or out of the interrupt struc- ture. In addition the entire interrupt system may be enabled or disabled under program control using a single instruction (except- ing power fail and parity error interrupts). Of the 60 interrupt levels, the two highest priority levels are re- served for hardware faults (power fail and parity error), the next two are reserved for DMA completion interrupts, and the remain- ing 56 are available for the I/O device channels. Table 2.3 lists interrupt levels in order of priority. Note that interrupt facilities for I/O channels above 25 (octal) are available through use of an I/O extender or multiplexer. CHANNEL INTERRUPT (Octal) LOCATION ASSIGNMENT 04 00004 Power Fail Interrupt 05 00005 Memory Parity/Protect Interrupt 06 00006 DMA Channel 1 Completion Interrupt 07 00007 DMA Channel 2 Completion Interrupt 10 00010 I/O Device, highest priority thru 25 00025 I/O Device, (Mainframe) thru 65 00065 I/O Device, (Extender) thru 77 00077 I/O Device, (Multiplexer) Table 2.3. Interrupt Assignments 2-12 Interrupt requests received while the computer is in halt mode will be processed, in order of priority, when the computer is put into run mode or is stepped single cycle. 2.5.1 POWER FAIL INTERRUPT The computer is equipped with power sensing circuits. When pri- mary power to the computer fails or drops below a safe operating level while the computer is running, an interurpt to memory loca- tion 00004 is automatically generated. This interrupt is given the highest priority in the system, and cannot be turned off or disabled. Location 00004 is intended to contain a jump-to-subroutine in- struction referencing the entry point of a shut-down program but it may alternatively contain a HLT instruction. Interrupt capability for lower-priority functions is automatically inhibited while a power fail routine is in progress. Sufficient time is available be- tween the detection of power failure and the loss of usable internal power to execute about 100 instrucions. The shut-down program should be written to save the current state of the computer system in memory, and then must halt the computer. A sample program is given in table 2.4 Since restoration of power might be unattended by an opera- tor, the user is given a switch-selectable option of what action the computer should take. With the switch set to the halt position, the computer will halt when power is restored, whether the com- puter was running or halted when the failure occured. (No panel indication is given.) With the switch in the restart position, the automatic restart feature is enabled. After a build-in delay of about a second following return to normal power levels, another inter- rupt is generated, again to location 00004. This time the shut-down portion of the subroutine is skipped (see sample subroutine) and the power-up portion begins. If the computer was not running when the power failure occured, the computer is halted. If the computer was running, the system conditions are restored and the computer continues operation from the point of interruption. Al- ternatively, if location 00004 contains a HLT instead of a jump to a subroutine, the computer will halt at this time and EXTERNAL PRESET (or PRESET on the controller panel) will light. To allow for the possibility of a second power failure occuring while the power-up routine is in progress, the user should limit the combined total of instructions (for both shut-down and power-up) 2-13 LABEL OPCODE OPERAND COMMENTS PFAR NOP Power fail/Auto Restart Subroutine SFC 4B Skip if interrupt was caused by a failure JMP UP Power is being restored, reset state of computer system DOWN STA SAVA Save A-register contents CCA Set switch indicating that the comp- STA SAVR uter was running when power failed STB SAVB Save B-register contents ERA,ALS Transfer E-register content to A- register bit 15 SOC Increment A-register if Overflow INA is set STA SAVEO Save E- and O-register contents LDA PFAR Save contents of P-register at time of STA SAVP of power failure LIA 1B Save contents of STA SAVP S-register . Insert user-written . routine to save . I/O device states CLC 4B Turn on restart logic so computer will restart when power is restored after momentary power failure HLT UP LDA SAVR Was computer running when SZA,RSS power failed? JMP HALT No CLA Yes, reset computer Run switch to STA SAVR to initial state LDA FENCE Restore the memory protect OTA 5B fence register contents . Insert user-written . routine to restore . I/O device states LDA SAVEO Restore the contents CLO of the SLA,ELA E-register STF 1B and O-register LDA SAVS Restore the contents of the OTA 1B S-register LDA SAVA Restore A-register contents LDB SAVB Restore B-register contents STC 4B Reset power fail logic for next power failure STC 5B Turn on memory protect JMP SAVP,I Transfer control to program in execution at time of power failure HALT HLT Return computer to halt mode SAVEO OCT 0 Storage for E and O SAVA OCT 0 Storage for A SAVB OCT 0 Storage for B SAVS OCT 0 Storage for S SAVP OCT 0 Storage for P SAVR OCT 0 Storage for Run switch Table 2.4. Sample Power Fail Subroutine 2-14 to less than 100. If the computer memory does not contain a sub- routine to service the interrupt, location 00004 should contain a HLT 04 instruction (octal 102004). A set control command (STC 04) must be given at the end of any restart routine. This command re-initializes the power fail logic and restores interrupt capability to lower priority functions. The EXTERNAL PRESET switch, when pressed, issues a similar command. 2.5.2 PARITY ERROR INTERRUPT Parity checking of memory is a standard feature of the 2100A Computer. The parity logic continuously generates correct parity for all words written into memory and monitors the parity of all word read out of memory. Correct parity is defined as having the total number of "1" bits in a 17-bit memory word equal to odd value. If a "1" bit (or any odd number of "1" bits) is either dropped or added in the transfer process, a parity error signal is generated when the word is read out. Unless the error logic is spe- cifally disabled by a CLF 05 instruction, the error signal causes an interrupt to location 00005. Optionally (switch-selectable) the error signal may cause a halt, rather than an interrupt. The lighting of the HALT and PARITY indicators signals the fact that the halt was caused by a parity error. The PARITY light stays on until INTERNAL PRESET is pressed. Assuming that the interrupt option is selected, the interrupt to location 00005 directs the computer to the entry point of a parity error subroutine. It is the user's decision as to what to do about a parity error; for example, he may want to record the address of the error location, or abort a critical operation. In any case, the PARITY light is turned off as soon as the interrupt is acknowledged and normal operation may be resumed on exit from the the subroutine. An STF 05 instruction should be given at the end of the subrou- tine to re-initialize the logic. In conjunction with the memory protect feature, it is possible to determine the address of the error location. The error address will automatically be loaded into the violation register of the memory 2-15 protect logic, and from there it is accessible to the progammer. (See following discussion of memory protect interrupt.) It is recommended on discovery of a parity error, that the entire program or set of data containing the error location be reloaded. However, knowing the address and contents of the error location, the user may be able to determine what operations have taken place as a result of reading the erroneous word. For example, if the word was an instruction, several other locations may be affected. By individually checking and correcting the contents of all affected locations, the user may resume running his program without a complete reload. If software is being generated, this may also need to be corrected. 2.5.3 MEMORY PROTECT INTERRUPT Memory protect for the 2100A Computer is a standard feature. With this capability a selected block of memory of any size, from a settable fence address downward, is protected against alteration by memory reference instructions (excluding A- and B-register ad- dresses, which may be freely addressed by any memory reference instruction except JMP). Also, when enabled, it prohibits the exe- cution of all I/O instructions except those referencing I/O address 01 switch and overflow registers. This second feature limits the control of input/output operations to interrupt control only. Then, by programming the system to direct all I/O interrupts to an execu- tive program in protected memory, the executive program can have exclusive control of the I/O system. The memory protect logic is disabled by any interrupt (except if the interrupt location contains an input/output group instruction) and is re-enabled by an STC 05 instruction at the end of each interrupt subroutine. In the halt mode, memory protect is also disabled by the INTERNAL PRESET switch. Programming rules pertaining to the use of memory protect, assum- ing the logic is enabled, are as follows: a. Location 00002 is the lower boundary of protected memory. Locations 00000 and 00001 are the A- and B-register addresses.) 2-16 b. JMP instructions may not reference the A- or B- registers. JSB, however, may do so. c. The upper boundary is loaded into the fence register from the A- or B-register by an OTA or OTB instruction with select code 05. Memory locations below (but not including) this address are protected. d. Execution will be inhibited and an interrupt to loca- tion 00005 will occur if a JMP, JSB, ISZ, STA, STB, or DST in- struction directly or indirectly addresses a location in protected memory, or if any I/O instruction is attempted (including halt, but excluding those addressing select code 01, the S- and overflow registers). e. Any instruction not mentioned in "d" is legal, even if it does reference protected memory. In addition, indirect ad- dressing through protected memory by those memory reference instructions listed in "d" is legal, provided the final effective ad- dress is outside protected memory. Following a memory protect interrupt, the address of the illegal instruction will be present in the violation register. This address is made accessible to the programmer by an LIA 05 or LIB 05 instruction, which loads the address into the A- or B-register. Since parity error and memory protect share the same interrupt locations, it is necessary to distinguish which type of error is re- sponsible for the interrupt. If, after the LIA/B instruction (pre- ceding paragraph), bit 15 of the A-/B-register is a "1," parity error is indicated; if bit 15 is a "0," memory protect violation is indi- cated. In either case, the remaining bits of the register give the address of the error location. Table 2.5 illustrates a sample memory protect and parity error sub- routine. An assumption made for this example is that the location following the error location is an appropriate return point. This may not always be the case; for example, it may be advisable to abort the program in progress and return to a supervisory program. 2-17 LABEL OPERATION COMMENTS ----- --------- -------- MPPE NOP Memory Protect/Parity Error Subroutine CLF 0 Turn off interrupt system to inhibit I/O devices CLF 5 Turn off P.E. interrupt during subroutine STA SVA Save A-register contents STB STB Save B-register contents LIA 5 Get contents of violation register in MP logic SSA Check bit 15 to determine kind of error JMP PERR If a 1, go to parity error routine JMP MPTR If a 0, go to memory protect routine * MPTR ... User's routine in case of memory protect violation ... ... LDA SVA Restore A-register LDB SVB Restore B-register STF 0 Enable interrupt system STF 5 Turn on parity error interrupt STC 5 Turn on memory protect interrupt JMP MPPE,I Exit the subroutine * PERR ... User's routine in case of parity error ... ... JMP PERR-6 Restore accumulators, turn on interrupts, exit Table 2.5. Sample Memory Protect/Parity Error Subroutine 2-18 2.5.4 INTERRUPTS The direct memory access (DMA) option provides high speed block transfers of data between I/O devices and memory. For the most part, DMA operates independently of the interrupt system. (Refer to the description of DMA operation in the Input/Output Section of this manual.) The only time that DMA generates an interrupt is when it has com- pleted transferring a specified block of data. Since there are two DMA channels, two interrupt locations are reserved for this option: location 00006 (interrupt from DMA channel 1) and location 00007 (interrupt from DMA channel 2). The channel 1 interrupt has priority over the channel 2 interrupt. Since these interrupts are primarily completion signals to the programmer and are there- fore application dependent, no subroutine example is given. 2.5.5 I/O INTERRUPTS The remaining interrupt locations (octal 00010 through 00077) are available to I/O devices. This represents a total of 56 (decimal) locations, one for each of 56 I/O channels. In typical input/output operation, the computer issues a program- med command (e.g., set control/clear flag instruction STC,C) to one or more external devices, causing these devices to begin their read or write operation. Each device will put data into (input) or take data from (output) the input/output buffer on each individual interface card. During this time, the computer may continue run- ning a program or may be programmed into a waiting loop to wait for a specific device. On completion of the read or write operation, each device returns an operation completed signal (flag) to the computer. The flags are passed through a priority network which allows only one device to be serviced regardless of the number of flags simultaneously present. The flag with the highest priority generates an interrupt signal at the end of the current machine cycle, except under any of the following circumstances. a. Interrupt system disabled or device interrupt disabled. b. JMP indirect or JSB indirect not sufficiently executed. These instructions inhibit all interrupts, except memory protect, 2-19 until the instruction (plus one phase of the succeeding instruction) is completed, or until at least three indirect references have occur- red. The memory protect interrupt for a jump violation will occur on completion of the execute phase, but the jump itself will be inhibited. c. Instructions in an interrupt location not sufficiently ex- ecuted, even if of lower priority. Any interrupt inhibits the entire interrupt system until at least two phases have been completed. (JMP indirect and JSB indirect will be fully executed.) d. Direct memory access option in process of transferring data. e. The current instruction is one which may affect the priorities of input/output devices (STC, CLC, STF, CLF). The interrupt in this case must wait until the end of the succeeding machine cycle. A set flag flip-flop inhibits all interrupt requests below it on the priority string (provided that the control flip-flop is also set). Once the flag flip-flop is cleared the next lower device can then interrupt. A service subroutine for any device can be interrupted only by a higher priority device; then, after the higher device is serviced, the interrupted subroutine may continue. In this way, it is possible for several service subroutines to be in a state of interruption at once time; each will be permitted to continue when the higher priority device is serviced. All service subroutines normally end with a JMP indirect instruction to return the computer to the point of interrupt. For the programmer, communication with I/O devices is simplified by the availability of standard driver routines. Hewlett-Packard furnishes an I/O driver as an accessory to each standard peripheral device supplied by HP. The drivers supplied by HP conform to the design specifications of the HP Basic Control System and are sub- sequently referred to as BCS drivers. BCS drivers can be integrated into an existing basic control system simply by adding the addi- tional driver to the system in a simple configuration process. BCS drivers generally have the following characteristics: a. I/O is overlapped with processing using the computer priority interrupt system. 2-20 b. Each driver may operate identical devices occupying different I/O locations. c. Provide status and error information to user and system I/O requests. d. Compatible with other modules of HP software such as the Input/Output Control (IOC) program and the FORTRAN I/O program called the Formatter. e. The object code for a BCS driver is relocatable binary. The modularity of the basic control system provides the user with a very flexible operating system. The functions of the modules can be illustrated by following the sequence of events through a series of I/O transfers. An input transfer is used as an example. See Figure 2.3. THe user or system I/O request is made to a unique entry point in the IOC program. After checking the request for validity, IOC ob- tains the memory address of the BCS driver for the requested de- vice. Control is transferred to the BCS driver and the input opera- tion is initiated. After initiation the BCS driver transfers control back to the user or system program. The program continues pro- cessing until the I/O device completes a single operation. At that time an interrupt request is generated, which forces transfer of control to the BCS driver once again. The data is tranferred be- tween the device and a specified memory buffer and the I/O device is commanded to do another operation. This process continues until all data has been tranferred and the user or system input request is satisfied. The equipment table (EQT) is a memory table created at configu- ration time to describe the hardware I/O channel of the device, the name and address of the I/O driver to be used, a status word, and a transmission log to be used by the I/O driver. Each physical I/O device (or sometimes, I/O subsystem consisting of two or more devices) in a system is defined by an entry in the EQT. The EQT provides the interface between IOC and the BCS driver and in addition provides for device independent programming. 2-21 Entry | | V --------------------- | | | INPUT/OUTPUT | | CONTROL |----+ | (IOC) | | | | | |---------------------| | | |<---+ | | | | EQU |<---+ | | | | |<---+ |---------------------| | | ------------------ | I/O DRIVER #1 |---------->| I/O DEVICE #1 | | | ------------------ |---------------------| | | ------------------ | I/O DRIVER #2 |---------->| I/O DEVICE #2 | | | ------------------ |---------------------| | | ------------------ | I/O DRIVER #3 |---------->| I/O DEVICE #3 | | | ------------------ --------------------- Figure 2.3. Modules of BCS 2.5.6 INTERRUPT REGISTER Each time an interrupt occurs, the address of the interrupt location is stored in the central interrupt register. The contents of this register is accessible at any time with an LIA 04 or LIB 04 instruc- tion. This puts the address of the most recent interrupt into the A- or B-register. 2.5.7 INTERRUPT SYSTEM CONTROL I/O address 00 is a master control address for the interrupt sys- tem. An STF 00 instruction enables the entire interrupt system, and a CLF 00 instruction disables the interrupt system. The two 2-22 exceptions are the power fail interrupt, which cannot be disabled, and parity error interrupt, which can only be selectively enabled or disabled by STF 05 or CLF 05, respectively. Whenever power is turned on, a clear signal to I/O address 00 auto- matically disables the interrupt system. The INTERRUPT SYSTEM pushbutton on the operator panel may be used to switch the inter- rupt system on or off manually. However, programs dependent on interrupt operation should include an STF 00 instruction to ensure that the interrupt system is enabled in the run mode. 2-23