INSTRUCTIONS This section defines each of the 80 machine instructions of the 2100A computer. Definitions are grouped according to instruction type: memory reference, register reference, input/output, extended arithmetic memory reference, and extended arithmetic register reference. With each definition is a diagram showing the machine coding of the instruction. The light shaded bits code the instruction type and the dark shaded bits code the specific instruction. Unshaded bits are further described under the introduction to each instruction type. The mnemonic code and instruction name are given above each diagram. In all cases where an additional bit is used to specify a secondary function (D/I, Z/C, or H/C), the choice is made by coding a logic 0 or 1 respectively. That is, a logic 0 codes D, Z, and H, and a logic 1 code I, C, and C. These abbreviations are defined as follows: D = Direct addressing I = Indirect addressing Z = Zero page C = Current page H = Hold flag C = Clear flag 3.1 INSTRUCTION TIMING All instructions except ISZ and the extended arithmetic instruc- tions are fully executed in 1.96 microseconds. ISZ is executed in 2.94 microseconds, and the extended arithmetic instructions are executed in the times shown in table 3.1. The Divide instruction executes faster than shown if the divisor is positive (15.68 micro- seconds) or if overflow occurs (11.76 microseconds). If indirect addressing is used with any of the single-word memory reference instructions, 0.98 microsecond is added for each level of indirect 3-1 addressing used; 1.96 microseconds are added for each level of indirect addressing with extended arithmetic memory reference instructions. Instructions are executed in two or more phases. The first phase is the fetch phase, which obtains an instruction from memory and transfers it into the central processor's instruction register. Next, there can be one or more indirect phases. The indirect phase, which applies only to single-length memory reference instructions, ob- tains a new operand address for the same (current) instruction. INSTRUCTION TIME (usec) MPY (Multiply) 10.78 DIV (Divide) Max 16.66 DLD (Double Load) 5.88 DST (Double Store) 5.88 Number of shifts ASR 1,2,3 2.94 (Arithmetic 4,5,6,7,8,9 3.92 Shift 9,10,11,12,13 4.90 Right) 14,15,16 5.88 ASL 1,2,3,4,5 4.90 (Arithmetic 6,7,8,9,10 5.88 Shift 11,12,13,14,15 6.86 Left) 16 7.84 LSR,RRR 1,2 2.94 (Logical 3,4,5,6,7 3.92 Shift Right, 8,9,10,11,12 4.90 Rotate Right) 13,14,15,16 5.88 LSL,RRL 1,2,3,4 4.90 (Logical 5,6,7,8,9 5.88 Shift Left, 10,11,12,13,14 6.86 Rotate Left) 15,16 7.84 Table 3.1. Extended Arithmetic Execution Times 3-2 Lastly, there is an execute phase, which accomplishes actual exe- cution of the instruction. For extended arithmetic memory refer- ence instructions, indirect addressing is also accomplished in the execute phase. Although the duration of a phase varies considera- bly (from 588 nanoseconds to an indeterminate time in the case of extended arithmetic indirect addressing), syncronization with memory or input/output operations results in overall execution times as specified in the preceding paragraph. 3.2 MEMORY REFERENCE INSTRUCTIONS The 14 memory reference instructions execute a function involving data in memory. Bits 0 through 9 specify the affected memory location on a given memory page or, if indirect addressing is used, the next address to be referenced. Indirect addressing may be con- tinued to any number of levels; when the D/I bit is "0" (specify- ing direct address), that location will be taken as the effective address. The A- and B-registers may be addressed as locations 00000 and 00001 (octal) respectively. If bit 10 (Z/C) is "0", the memory address is on page zero; If bit 10 is a "1", the memory address is on the current page. If the A- or B-register is addressed, bit 10 must be a "0" to specify page zero, unless the current page is page zero. AND "AND" TO A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | |---|-----------|-----------|-----------|-----------|-----------| |D/I| 0 0 1 | 0 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- The contents of the addressed location is logically "anded" to the contents of the A-register. The contents of the memory is left unaltered. JSB JUMP TO SUBROUTINE ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| 0 0 1 | 1 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- 3-3 This instruction, executed in location P, causes the computer control to jump unconditionally to the memory location (m) specified in the address portion of the JSB instruction word. The contents of the P-register plus one (return address) is stored in location m, and the next instruction to be executed will be that contained in the next location (m + 1). A return to the main program sequence at P + 1 may be effected by a jump indirect through location m. XOR "EXCLUSIVE OR" TO A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| 0 1 0 | 0 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- The contents of the addressed location is combined with the con- tents of the A-register as an "exclusive or" logic operation. The contents of the memory is left unaltered. JMP JUMP ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| 0 1 0 | 1 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- The instruction transfers control to the addressed location. That is, JMP causes the P-register to be set according to the memory address portion of the instruction word, so that the next instruc- tion will be read from that location. IOR "INCLUSIVE OR" TO A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| 0 1 1 | 0 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- The contents of the addressed location is combined with the con- tents of the A-register as an "inclusive or" logic operation. The contents of the memory cell is left unaltered. 3-4 ISZ INCREMENT AND SKIP IF ZERO ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| 0 1 1 | 1 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- An ISZ instruction adds one to the contents of the addressed mem- ory location. If the result of this operation is zero, the next instruc- tion is skipped; i.e., the P-register is advanced by two instead of one. Otherwise, the program proceeds normally to the next instruc- tion in sequence. The incremented value is written back into the memory cell in either case. An ISZ instruction referencing loca- tions zero or one (A- or B-register) cannot cause setting of the extend or overflow bits (unlike INA and INB). ADA ADD TO A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| 1 0 0 | 0 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- The contents of the addressed memory location is added to the contents of the A-register, and the sum remains in the A-register. The result of the addition may set the extend or overflow bits. The contents of the memory cell is unaltered. ADB ADD TO B ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| 1 0 0 | 1 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- The contents of the addressed memory location is added to the contents of the B-register, and the sum remains in the B-register. Extend or overflow bits may be set, as for ADA. The contents of the memory cell is unaltered. 3-5 CPA COMPARE TO A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| 1 0 1 | 0 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- The contents of the addressed location is compared with the con- tents of the A-register. If the two 16-bit words are unequal, the next instruction is skipped; i.e., the P-register is advanced by two instead of one. If the words are identical, the program proceeds normally to the next instruction in sequence. The contents of neither the A-register nor the memory cell is altered. CPB COMPARE TO B ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| 1 0 1 | 1 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- Same as CPA, except comparison is made with the B-register. LDA LOAD A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| 1 1 0 | 0 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- The A-register is loaded with the contents of the addressed loca- tion. The contents of the memory cell is unaltered. LDB LOAD B ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| 1 1 0 | 1 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- The B-register is loaded with the contents of the addressed loca- tion. The contents of the memory cell is unaltered. 3-6 STA STORE A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| 1 1 1 | 0 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- The contents of the A-register is stored in the addressed location. The previous contents of the memory cell is lost; the A-register is unaltered. STB STORE B ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| 1 1 1 | 1 Z/C | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ---------- Memory Address --------- The contents of the B-register is stored in the addressed location. The previous contents of the memory cell is lost; the B-register is unaltered. 3.3 REGISTER REFERENCE INSTRUCTIONS The 39 register reference instructions execute various functions on data contained in the A-, B- and E-registers. The instructions are divided into two groups: the shift-rotate group and the alter-skip group. In each group, several instructions may be combined into one word and are thus individually termed microinstructions. Since the two groups are separate and distinct, microinstructions from the two groups cannot be mixed. Unshaded bits in the coding dia- grams are available for combining other microinstructions. SHIFT-ROTATE GROUP. The 20 instructions of the shift-rotate group are defined first. A comparison of shift and rotate functions is given in figure 3.1. Rules for combining microinstructions are as follows. (refer to table 3.2) a. Only one microinstruction can be chosen from the multiple choice column. 3-7 b. References to A- and B-registers cannot be mixed. c. The sequence of execution is left to right. d. In machine code, use zeros to exclude unwanted micro- instruction bits. e. Use a "1" bit in bit 9 to enable shifts and rotates in the first position, and a "1" in bit 4 to enable shifts or rotates in the second position. f. The extend bit is not affected unless specifically stated. However, if a rotate-with-E instruction (ERA/B, ELA/B) is coded but disabled by a "0" in bit 9 or 4, the E-register will be updated even though the A- or B-register is not affected; code a NOP (three zeros) to avoid this situation. --------------------------------- | | | ALS ALS | | ARS ARS | | RAL RAL | | RAR , CLE , SLA , RAR | | ALR ALR | | ALF ALF | | ELA ELA | | ERA ERA | | | |---------------------------------| | | | BLS BLS | | BRS BRS | | RBL RBL | | RBR , CLE , SLB , RBR | | BLR BLR | | BLF BLF | | ELB ELB | | ERB ERB | | | --------------------------------- Table 3.2. Shift-Rotate Combining Guide NOP NO OPERATION ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 0 0 | 0 0 0 | 0 0 0 | 0 0 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- An all-zero instruction word causes a no-operation cycle. 3-8 ALS BLS ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- BEFORE: |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | / / / / / / / / / / / / / / | / / / / / / / / / / / / / / 0 | / / / / / / / / / / / / / / / ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- AFTER: |15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- ARS BRS ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- BEFORE: |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- AFTER: |15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- RAL RBL ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- BEFORE: |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- To bit / / / / / / / / / / / / / / / / From 0 --> / / / / / / / / / / / / / / / >-- bit / / / / / / / / / / / / / / / / 15 ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- AFTER: |15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- RAR RBR ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- BEFORE: |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- From \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ To bit --< \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ <-- bit 0 \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 15 ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- AFTER: |15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- ALR BLR ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- BEFORE: |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- / / / / / / / / / / / / / / 0 / / / / / / / / / / / / / / 0 \ / / / / / / / / / / / / / / / ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- AFTER: |15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- ERA ERB ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- BEFORE: |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- From \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ To E -- \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ -- E bit \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ bit ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- AFTER: |15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- ELA ELB ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- BEFORE: |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- To / / / / / / / / / / / / / / / / From E -- / / / / / / / / / / / / / / / -- E bit / / / / / / / / / / / / / / / / bit ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- AFTER: |15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- ALF BLF ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- BEFORE: |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- / / / / / / / / / / / / / / / / From ------------ ------------ ------------ ------------ >>- bits To / / / / / 12-15 bits -->> ------------ ------------ ------------ ------------ 0-3 / / / / / / / / / / / / / / / / ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- AFTER: |15 |14 13 12 |11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Figure 3.1. Shift and Rotate Functions 3-9 CLE CLEAR E ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 | | 1 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Clear E-register (extend bit). SLA SKIP IF LSB OF A IS ZERO ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 0 | | 1 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- The next instruction is skipped if the least significant bit of the A-register is "0". SLB SKIP IF LSB OF B IS ZERO ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 0 | | 1 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- The next instruction is skipped if the least significant bit of the B-register is "0". ALS A LEFT SHIFT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 0 1 | 0 0 0 | 1 | 0 0 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position The A-register is arithmetically shifted left one place, 15 magnitude bits only. Bit 15 (sign bit) is not affected; bit shifted out of bit 14 is lost. A "0" replaces vacated bit 0. 3-10 BLS B LEFT SHIFT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 0 1 | 0 0 0 | 1 | 0 0 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position The B-register is arithmetically shifted left one place, 15 magnitude bits only. Bit 15 (sign bit) is not affected; bit shifted out of bit 14 is lost. A "0" replaces vacated bit 0. ARS A RIGHT SHIFT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 0 1 | 0 0 1 | 1 | 0 0 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position The A-register is arithmetically shifted right one place, 15 magni- tude bits only. Bit 15 (sign bit) is not affected; copy of sign bit is shifted into bit 14. Bit shifted out of bit 0 is lost. BRS B RIGHT SHIFT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 0 1 | 0 0 1 | 1 | 0 0 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position The B-register is arithmetically shifted right one place, 15 magni- tude bits only. Bit 15 (sign bit) is not affected; copy of sign bit is shifted into bit 14. Bit shifted out of bit 0 is lost. 3-11 RAL ROTATE A LEFT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 0 1 | 0 1 0 | 1 | 0 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position Rotate A-register left one place, all 16 bits. Bit 15 is rotated around to bit 0. RBL ROTATE B LEFT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 0 1 | 0 1 0 | 1 | 0 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position Rotate B-register left one place, all 16 bits. Bit 15 is rotated around to bit 0. RAR ROTATE A RIGHT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 0 1 | 0 1 1 | 1 | 0 1 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position Rotate A-register right one place, all 16 bits. Bit 0 is rotated around to bit 15. 3-12 RBR ROTATE B RIGHT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 0 1 | 0 1 1 | 1 | 0 1 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position Rotate B-register right one place, all 16 bits. Bit 0 is rotated around to bit 15. ALR A LEFT SHIFT, CLEAR SIGN ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 0 1 | 1 0 0 | 1 | 1 0 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position Shift A-register left one place, same as ALS, but clear sign bit after shift. BLR B LEFT SHIFT, CLEAR SIGN ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 0 1 | 1 0 0 | 1 | 1 0 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position Shift B-register left one place, same as BLS, but clear sign bit after shift. 3-13 ERA ROTATE E RIGHT WITH A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 0 1 | 1 0 1 | 1 | 1 0 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position Rotate E-register right with A-register, one place (17 bits). Bit 0 is rotated into extend register; extend contents is rotated into bit 15. ERB ROTATE E RIGHT WITH B ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 0 1 | 1 0 1 | 1 | 1 0 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position Rotate E-register right with B-register, one place (17 bits). Bit 0 is rotated into extend register; extend contents is rotated into bit 15. ELA ROTATE E LEFT WITH A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 0 1 | 1 1 0 | 1 | 1 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position Rotate E-register left with A-register, one place (17 bits). Bit 15 is rotated into extend register; extend contents is rotated into bit 0. 3-14 ELB ROTATE E LEFT WITH B ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 0 1 | 1 1 0 | 1 | 1 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position Rotate E-register left with B-register, one place (17 bits). Bit 15 is rotated into extend register; extend contents is rotated into bit 0. ALF ROTATE A LEFT FOUR ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 0 1 | 1 1 1 | 1 | 1 1 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position Rotate A-register left four places, all 16 bits. Bits 15,14,13,12 are rotated around to bits 3,2,1,0 respectively. Equivalent to four successive RAL instructions. BLF ROTATE B LEFT FOUR ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 0 1 | 1 1 1 | 1 | 1 1 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | | | | | | | | +---+---+---+ +-------+---+---+ 1st position 2nd Position Rotate B-register left four places, all 16 bits. Bits 15,14,13,12 are rotated around to bits 3,2,1,0 respectively. Equivalent to four successive RBL instructions. ALTER-SKIP GROUP. The 19 instructions of the alter-skip group are defined next. This group is specified by a "1" bit in bit 10. 3-15 Rules for combining microinstructions are as follows. (Refer to table 3.3) a. Only one micro-instruction can be chosen from the multi-choice columns. b. References to A- and B-registers cannot be mixed. c. The sequence of execution is left to right. d. If two or more skip functions are combined, the skip will occur if either or both conditions are met. One exception exists: refer to RSS instruction. e. In machine code, use zeros to exclude unwanted micro instruction bits. ---------------------------------------------------- | | | CLA CLE | | CMA , SEZ , CME , SSA , SLA , INA , SZA , RSS | | CCA CCE | | | |----------------------------------------------------| | | | CLB CLE | | CMB , SEZ , CME , SSB , SLB , INB , SZB , RSS | | CCB CCE | | | ---------------------------------------------------- Table 3.3. Alter Skip Combining Guide CLA CLEAR A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 1 0 | 1 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Clear the A-register. 3-16 CLB CLEAR B ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 1 0 | 1 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Clear the B-register. CMA COMPLEMENT A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 1 1 | 0 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Complement the A-register (One's complement.) CMB COMPLEMENT B ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 1 1 | 0 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Complement the B-register (One's complement.) CCA CLEAR AND COMPLEMENT A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 1 1 | 1 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Clear, then complement the A-register. Puts 16 one's in the A- register; this is the two's complement form of -1. CCB CLEAR AND COMPLEMENT B ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 1 1 | 1 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Clear, then complement the B-register. Puts 16 one's in the B- register; this is the two's complement form of -1. 3-17 CLE CLEAR E ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 | 0 1 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Clear the E-register (extend bit). CME COMPLEMENT E ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 | 1 0 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Complement the E-register (extend bit). CCE CLEAR AND COMPLEMENT E ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 | 1 1 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Clear, then complement the E-register (extend bit). Sets the extend bit to "1". SEZ SKIP IF E IS ZERO ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 | | 1 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Skip the next instruction if the E-register (extend bit) is zero. SSA SKIP IF SIGN OF A IS ZERO ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 1 | | 1 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Skip the next instruction if the sign bit (bit 15) of the A-register is zero; i.e., skip if the contents of A is positive. 3-18 SSB SKIP IF SIGN OF B IS ZERO ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 1 | | 1 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Skip the next instruction if the sign bit (bit 15) of the B-register is zero; i.e., skip if the contents of B is positive. SLA SKIP IF LSB OF A IS ZERO ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 1 | | 1 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Skip the next instruction if the least significant of the A-register is zero; i.e., skip if an even number is in A. SLB SKIP IF LSB OF B IS ZERO ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 1 | | 1 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Skip the next instruction if the least significant of the B-register is zero; i.e., skip if an even number is in B. INA INCREMENT A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 1 | | | 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Increment the A-register by one. Can cause setting of extend or overflow bits. INB INCREMENT B ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 1 | | | 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Increment the B-register by one. Can cause setting of extend or overflow bits. 3-19 SZA SKIP IF A IS ZERO ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 0 1 | | | 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Skip the next instruction if the A-register is zero (16 zeros). SZB SKIP IF B IS ZERO ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 1 | | | 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Skip the next instruction if the B-register is zero (16 zeros). RSS REVERSE SKIP SENSE ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 0 | 0 0 0 | 1 | | | 0 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Skip occurs for any of the preceding skip instructions, if present, when the non-zero condition is met. RSS without a skip instruciotn in the word causes an unconditional skip. If a word with RSS also includes both SSA/B and SLA/B bits 15 and 0 must both be one for skip to occur. In all other cases the skip occurs if one or more skip condition is met. 3.4 INPUT/OUTPUT INSTRUCTIONS The 17 input/output instructions provide the capability to set or clear the I/O flag and conrtol bits and the overflow bit, to test the state of the overflow and I/O flag bits, and to transfer data between an I/O channel and the A- and B- registers. In addition, specific instructions in this group control the interrupt system and can cause a programmed halt. Bit 11, where relevant, specifies the A- or B-register or distinguishes between set control and clear control; otherwise it may be "1" or "0" without affecting the instruciton (although the assemblier will assign zeros, as shown). Bit 9, where not specified, offers the choice 3-20 of holding (0) or clearing (1) the device flag after execution of the instruction. (Exception: the H/C bit associated with the last two instructions in this list holds or clears the overflow bit instead of a flag bit.) Bits 8, 7 and 6 identify the instruction. Bits 5 through 0 (unshaded) form select codes to make the instruction apply to one of up to 64 input/output devices or functions. HLT HALT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 1 H/C| 0 0 0 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / --- Select Code --- Halts the computer and holds or clears the flag (according to bit 9) of any desired input/output device (bits 5 through 9). The HLT instruction has the same effect as the HALT pushbutton: the HALT switch lights, and the front-panel control switches are enabled. The HLT instruction will be displayed (MEMORY DATA is auto- matically selected when computer halts), and the P-register will normally indicate the halt location plus one. STF SET FLAG ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 1 0 | 0 0 1 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / --- Select Code --- Set the flag of the selected I/O channel or function. An STF 00 instruction enables the interrupt system for all select codes (ex- cept power fail and parity error, which are always enabled). CLF CLEAR FLAG ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 1 1 | 0 0 1 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / --- Select Code --- Clears the flag of the selected I/O channel or function. A CLF 00 3-21 instruction disables the interrupt system for all select code (ex- cept power fail and parity error, which are always enabled); this does not affect the status of the individual channel flags. SFC SKIP IF FLAG CLEAR ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 1 0 | 0 1 0 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / --- Select Code --- Skip next instruction if the flag of the selected channel is clear (device busy). SFS SKIP IF FLAG SET ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 1 0 | 0 1 1 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / --- Select Code --- Skip the next instruction is the flag of the selected channel is set (device ready). MIA MERGE INTO A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 1 | 1 0 0 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / --- Select Code --- The contents of the input/output buffer associated with the selec- ted device is merged ("inclusive or") into the A-register. 3-22 MIB MERGE INTO B ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 1 1 | 1 0 0 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / --- Select Code --- The contents of the input/output buffer associates with the selec- ted device is merged ("inclusive or") into the B-register. LIA LOAD INTO A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 1 | 1 0 1 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / --- Select Code --- The contents of the input/output buffer associated with the selec- ted device is loaded into the A-register. LIB LOAD INTO B ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 1 1 | 1 0 1 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / --- Select Code --- The contents of the input/output buffer associated with the selec- ted device is loaded into the B-register. OTA OUTPUT A ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 1 | 1 1 0 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / --- Select Code --- The contents of the A-register is loaded into the input/output buffer associated with the selected device. If the buffer is less than 16 bits in length, the least significant bits of the A-register normally 3-23 are loaded. (Some exceptions exist, depending on the type of out- put device.) A-register contents is not altered. OTB OUTPUT B ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 1 1 | 1 1 0 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / --- Select Code --- The contents of the B-register is loaded into the input/output buffer associated with the selected device. STC SET CONTROL ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 1 | 1 1 1 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / --- Select Code --- Sets the control bit of the selected I/O channel or function. CLC CLEAR CONTROL ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 1 1 | 1 1 1 | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / --- Select Code --- Clears the control bit of the selected I/O channel or function. This turns off a device channel and prevents it from interrupting. A CLC 00 instruction clears all control bits from select code 06 and up, effectively turning off all I/O devices. STO SET OVERFLOW ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 1 0 | 0 0 1 | 0 0 0 | 0 0 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Sets the overflow bit. 3-24 CLO CLEAR OVERFLOW ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 1 1 | 0 0 1 | 0 0 0 | 0 0 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Clears the overflow bit. SOS SKIP IF OVERFLOW SET ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 1 H/C| 0 1 1 | 0 0 0 | 0 0 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- If the overflow register is set, the next instruction of the program is skipped. Use of H/C bit will hold or clear the overflow bit following execution of this instruction (whether the skip is taken or not). SOC SKIP IF OVERFLOW CLEAR ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 1 H/C| 0 1 0 | 0 0 0 | 0 0 1 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- If the overflow register is clear, the next instruction of the program is skipped. Use of H/C bit will hold or clear the overflow bit following execution of this instruction (whether the skip is taken or not). 3.5 EXTENDED ARITHMETIC MEMORY REFERENCE INSTRUCTIONS The four extended arithmetic memory reference instrucitons pro- vide for integer multiply and divide, and for loading and storing double-length words to and from the accumulators. The complete instruction requires two words: one for the instruction code, and one for the address. When stored in memory the instruction word is the first to be fetched; the address word is in the next higher location. 3-25 Since 15 bits are available for the address, these instructions may directly address any location in memory. As for all memory refer- ence instructions, indirect addressing to any number of levels may also be used. A "0" in the D/I bit specifies direct addressing; a "1" specifies indirect addressing. MPY MULTIPLY ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 0 0 | 0 1 0 | 0 0 0 | 0 0 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| | | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ------------------- Memory Address -------------------- Multiples a 16-bit integer in the A-register by a 16-bit integer in the addressed memory location. The resulting double-length integer product resides in the B- and A-registers, with the B-register con- taining the sign bit and the most significant 15 bits of the quantity. The A-register may be used as an operand (i.e., memory address 0), resulting in a arithmetic square. Overflow cannot occur; the in- struction clears the overflow bit. DIV DIVIDE ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 0 0 | 1 0 0 | 0 0 0 | 0 0 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| | | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ------------------- Memory Address -------------------- Divides a doubleword integer in the combined B- and A-registers by a 16-bit integer in the addressed memory location. The result is a 16-bit integer quotient in the A-register and a 15-bit integer remainder in the B-register. Overflow can result from an attempt to divide by zero, or from an attempt to divide by a number too small for the dividend. In the former case (divide by zero) execu- tion will be attempted with unpredicable results left in the B- and A-registers. In the latter case (divisor too small) the division will not be attemped and the B- and A-register contents will be un- changed except that a negative quantity will be made positive. If there is no divide error, the overflow bit is cleared. 3-26 DLD DOUBLE LOAD ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 1 0 0 | 0 1 0 | 0 0 0 | 0 0 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| | | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ------------------- Memory Address -------------------- Loads the contents of addressed memory location m (and m+1) into the A- and B-registers, respectively. DST DOUBLE STORE ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 1 0 0 | 1 0 0 | 0 0 0 | 0 0 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |D/I| | | | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ / ------------------- Memory Address -------------------- Stores the doubleword quantity in the A- and B-registers into ad- dressed memory locations m (and m+1), respectively. 3.6 EXTENDED ARITHMETIC REGISTER REFERENCE INSTRUCTIONS The six extended arithmetic register reference instructions provide various type of shifting operations on the combined contents of the B- and A- registers. The B-register is considered to be on the left (most significant word) and the A-register is considered to be on the right (least significant word). An example of each type of shift operation is illustrated in figure 3.2. The complete instruction is given in one word and includes four bits (unshaded) to specify the number of shifts, from 1 to 16. By viewing the four bits as a binary coded number, the number of shifts is easily expressed; e.g., binary-coded 1 for one shift, binary- coded 2 for two shifts, etc. The maximum of 16 shifts is coded with four zeros; this essentially exchanges the B- and A-register contents. The extend bit is not affected by any of the following instructions. Except for the arithmetic shifts, overflow also is not affected. 3-27 ---- B-REGISTER ----- ---- A-REGISTER ----- ASR 5 (Arithmetic Shift BEFORE: 1 011 000 101 000 101 0 101 101 011 100 111 Right 5 Places) AFTER: 1 111 110 110 011 010 0 010 101 011 010 111 ASL 5 (Arithmetic Shift BEFORE: 0 000 000 111 101 000 1 101 101 000 110 111 Left 5 Places) AFTER: 0 011 110 100 011 011 0 100 011 011 100 000 LSR 5 (Logical Shift BEFORE: 1 011 000 101 000 101 0 101 101 011 100 111 Right 5 Places) AFTER: 0 000 010 110 001 010 0 010 101 011 010 111 LSL 5 (Logical Shift BEFORE: 0 101 000 111 101 000 1 101 101 000 110 111 Left 5 Places) AFTER: 0 011 110 100 011 011 0 100 011 011 100 000 RRR 8 (Rotate Right BEFORE: 0 101 110 111 000 010 0 100 010 110 000 111 8 Places) AFTER: 1 000 011 101 011 101 1 100 001 001 000 101 RRL 7 (Rotate Left BEFORE: 0 110 011 101 111 000 0 110 011 010 000 111 7 Places) AFTER: 1 011 110 000 110 011 0 100 001 110 110 011 Figure 3.2. Examples of Doubleword Shifts and Rotates 3-28 ASR ARITHMETIC SHIFT RIGHT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 0 1 | 0 0 0 | 0 1 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ Number / -of shifts- Arithmetically shifts the combined contents of the B- and A- registers right, n places. The value of n may be any number from 1 through 16. The sign bit is unchanged and is extended into bit positions vacated by the right shift. Data bits shifted out of the least significant end of the A-register are lost. Overflow cannot occur; the instruction clears the overflow bit. ASL ARITHMETIC SHIFT LEFT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 0 1 | 0 0 0 | 0 1 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ Number / -of shifts- Arithmetically shifts the combined contents of the B- and A- registers left, n places. The value of n may be any number from 1 through 16. Zeros are filled into vacated low order positions of the A-register. The sign bit is unchanged, and data bits are lost out of bit 14 of the B-register. If one of the bits lost is a significant data bit ("1" for positive numbers, "0" for negative numbers), over- flow will be set; otherwise, overflow will be cleared during execu- tion. See ASL example in figure 3.2. (Note that two additional shifts in this example would cause an error by losing a significant "1". LSR LOGICAL SHIFT RIGHT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 0 1 | 0 0 0 | 1 0 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ Number / -of shifts- Arithmetically shifts the combined contents of the B- and A- registers right, n places. The value of n may be any number from 1 3-29 16. Zeros are filled into vacated high order bit positions of the B- register, and data bits are lost out of the low order bit positions of the B-register LSL LOGICAL SHIFT LEFT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 0 0 | 0 0 0 | 1 0 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ Number / -of shifts- Logically shifts the combined contents of the B- and A-registers left, n places. The value of n may be any number from 1 through 16. Zeroes are filled into vacated low order bit positions of the A- register, and data bits are lost out of the high order bit positions of the B-register. RRR ROTATE RIGHT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 0 1 | 0 0 1 | 0 0 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ Number / -of shifts- Rotates the combined contents of the B- and A-registers right, n places. The value of n may be any number from 1 through 16. No bits are lost or filled in. Data bits shifted out of the low order end of the A-register are rotated around to enter the high order end of the B-register. RRL ROTATE LEFT ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- |15 |14 13 12 | 11 10 9 | 8 7 6 | 5 4 3 | 2 1 0 | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | 1 | 0 0 0 | 0 0 0 | 0 0 1 | 0 0 | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- \ Number / -of shifts- Rotates the combined contents of the B- and A-registers left, n places. The value of n may be any number from 1 through 16. No bits are lost or filled in. Data bits shifted out of the high order end of the B-register are rotated around to enter the low order end of the A-register. 3-30 3.7 FLOATING POINT INSTRUCTIONS (Optional) Each of the six floating point instructions has a unique machine code associated with it. When a floating point instruction is assem- bled, the assembler places the appropriate machine code in the program. FORTRAN and ALGOL Compilers generate a subroutine call to the Program Library. The Library replaces the subroutine call with the appropriate machine code. Thus the Library is used only once. Execution of floating point machine code calls the ap- propriate firmware routine which allows the micro processor to execute the instruction. A complete summary of 2100 floating point instructions is given in table 3.4. DATA FORMAT Fixed Point: 15 14 0 ----------------------------- | | | ----------------------------- Sign Integer Floating Point: 15 14 0 15 8 7 1 0 ---------------------------------------------------------------- | | | | | ---------------------------------------------------------------- mag magnitude Exponent Exp sign Sign INSTRUCTION ADD SUBTRACT MULTIPLY PURPOSE to add two to subtract the to multiply two floating point floating point floating point numbers, x number y from numbers, x and y the floating and y point number x MACHINE CODE 105000B 105020B 105040B CALLING FAD FSB FMP SEQUENCE DEF Y [,I] DEF Y [,I] DEF Y [,I] ASSEMBLY FAD Y FSB Y FMP Y LANGUAGE (X is assumed to be in the A,B registers) RETURN Floating point result is left in the A,B registers MINIMUM EXE- 23.52 usec 24.50 usec 33.32 usec CUTION TIME (including Fetch) MAXIMUM EXE- 59.78 usec 60.76 usec 41.16 usec CUTION TIME EXECUTION .98 usec .98 usec .98 usec TIME FOR EACH LEVEL OF INDIRECT ERROR If the result is outside the range of representable CONDITION floating point numbers, [-2**127..2**127] the overflow flag is set and the result 2**128 is returned. If an underflow occurs, (result within the range -2**-129 to 2**-129), the overflow flag is set and the result 0 is returned. 3-31 INSTRUCTION DIVIDE FIX FLOAT PURPOSE to divide the to convert the to convert the floating point floating point integer i to number x by the number x to floating point floating point integer format format number y MACHINE CODE 105060B 105100B 105120B CALLING FDV FIX FLT SEQUENCE DEF Y [,I] ASSEMBLY FDV Y FIX FLT LANGUAGE (X is assumed to be in (I is assumed to be the A,B registers) in the A register) RETURN Floating point Integer result is Floating point result is left in left in A register. result is left the A,B registers Any fractional in the A,B part is truncated. registers B register content is meaningless. MINIMUM EXE- 51.94 usec 5.88 usec 9.80 usec CUTION TIME (including Fetch) MAXIMUM EXE- 55.86 usec 8.82 usec 24.50 usec CUTION TIME EXECUTION .98 usec --- --- TIME FOR EACH LEVEL OF INDIRECT ERROR Same as If the magnitude None CONDITION previous of the floating page point number is >= 2**15, the integer 32767 is returned and over- flow flag is set. If the magnitude of the floating point number is <= 1, the integer 0 is returned. 3-32