INPUT/OUTPUT SYSTEM The purpose of the input/output system is to transfer data between the computer and external devices. Normally, data is transferred through the A- or B-register. Refer to figure 4.1. This type of transfer occurs in three distinct steps: a. between external device and its interface card in the computer; b. between the interface card and the A- or B-register; and c. between the A- or B-register and memory. This three-step process applies to both the "in" direction (as above) and the "out" direction (reverse order). This type of transfer, which is executed under program control, allows the computer logic to manipulate the data during the transfer process. Data may also be transferred automatically under control of the direct memory access (DMA) option. Once the DMA option has been initialized, no programming is involved, and the transfer is reduced to a two-step process: the transfer between the device and its interface, and the transfer between the interface and memory. Two DMA channels are provided and are assignable to operate with any two device interfaces. Since the DMA transfer eliminates programmed loading and storing via the accumulators, the time involved is very short. Thus DMA is used with high-speed devices capable of transferring data at rates up to 1,020,400 sixteen-bit words per second. Further information on the direct memory access option is given later in this section. 4.1 I/O ADDRESSING As shown in figure 4.2, an external device is connected by a cable directly to an interface card located inside the computer. The 4-1 ----------- | | | CORE |----------------------------------+ | MEMORY | | | | | ----------- ----------- | | | | | DMA | ----------- | OPTION | | | | | | LOGIC | ----------- | | | | | | | | ----------- | | | | | +--------+--------+ | | | | | | --------- --------- | | | A | | B | | | --------- --------- | | | | I/O Bus | | =============================================================== | | | | | ----------- ----------- ----------- ----------- ----------- | I/O | | I/O | | I/O | | I/O | | I/O | | Interface | | Interface | | Interface | | Interface | | Interface | ----------- ----------- ----------- ----------- ----------- | | | | | | | | | | ----------- ----------- ----------- ----------- ----------- | Device | | Device | | Device | | Device | | Device | | 10 | | 11 | | 12 | | 13 | | 14 | ----------- ----------- ----------- ----------- ----------- Figure 4.1. Input/Output System interface card, in turn, plugs into one of the 14 input/output slots. Each slot is assigned a fixed address, called the select code. The computer can then communicate with a specific device on the basis of its select code. 4-2 priority, its interface and cable may be exchanged with those oc- cupying some other I/O slot. This will change both the priority and the I/O address. However, due to priority chaining (explained later), there can be no vacant slots from select code 10 to the highest used select code (if the interrupt mode is to be used). Only select code 10 through 77 (octal) are available for input/ output devices. The lower select codes (00 through 07) are re- served for other features discussed elsewhere in this manual. As figure 4.2 shows, select codes 10 through 25 are available in the mainframe of the computer. If an I/O extender is used, slot 25 is used for interconnection of the extender, and select codes 25 through 65 will then be available in the extender. This is a total of 45 (decimal) select codes. The full range of 56 select codes may be plugged into any slot, but the rule that there can be no vacant slots (select codes) from 10 upward must be maintained. Figure 4.2. I/O Address Assignments 4-3 In some cases, certain devices may require two I/O slots and two select codes. This requirement is fully explained in documentation supplied with the applicable interface. 4.2 I/O PRIORITY When a device is ready to be serviced (refer to "I/O Data Transfer"), it causes its interface to request an interrupt so that the computer will interrupt the current program and service the device. Since many device interfaces will be requesting service at random times, it is necessary to establish an orderly sequence for granting inter- rupts. Secondly, it is desireable that high-speed devices should not have to wait for low-speed device transfers. Both of these requirements are met by a series-linked priority structure, illustrated in simplified form in figure 4.3. The bold line, representing a priority enabling signal, is routed in series through each card which is capable of causing an interrupt. The car may not interrupt unless this enabling signal is present at its input. Each device (orother interrupt function) can break the enabling line when it requests an interrupt. If two devices simultaneously request an interrupt, obviously the device with the lowest select code number will be the first one which can interrupt, since it has broken the enable line for the higher select codes. The other device cannot begin its service routine until the first device is finished; however, a still higher priority device (lower select code) may interrupt the service routine of the first device. Figure 4.4 illustrates a hypothetical case in which several devices require servicing by interrupting a CPU program. Both simultane- ous and time-separate interrupt requests are considered. Assume that the computer is running a CPU program when an in- terrupt from I/O channel 12 occurs (at reference time t1). A JSB instruction in the interrupt location for select code 12 causes a program jump to the service routine for the channel 12 device. The JSB instruction automatically saves the return address (in a location which the programmer must reserve in his routine) for a later return to the CPU program 4-4 Figure 4.3. Priority Linkage 4-5 Figure 4.4. Interrupt Sequences 4-6 The routine for channel 12 is not completed when several other devices request service (set flag). First, channels 13 and 14 request simultaneously at t2; however, neither has priority over channel 12, so their flags are ignored and channel 12 continues its transfer. But at t3, a higher priority device on channel 10 requests service. This request interrupts the channel 12 transfer and causes the channel 10 transfer to begin. The JSB intruction saves the return address for return to the channel 12 routine. During the channel 10 transfer, device 11 sets the channel 11 flag (t4). Since it has lower priority than channel 10, device 11 must wait until the end of the channel 10 routine. And since channel 10, when it ends, contains a return address to the channel 12 routine, program control temporarily returns to channel 12 (even though the waiting channel 11 has higher priority). The JMP,I instruction used for the return inhibits all interupts until fully executed (plus one phase of the next instruction). At the end of this short interval, the channel 11 interrupt request is granted. When channel 11 has finished its routine, it returns control to channel 12, which at last has sufficient priority to complete its routine. Since channel 12 has been saving a return address in the main CPU program, it returns control to this point. The two waiting interrupt requests from channels 13 and 14 are now enabled. Since channel 13 has higher priority, it goes first. At the end of its routine, it temporarily returns control to the CPU program. Then the lowest priority channel, 14, interrupts and com- pletes its transfer. Finally, control is returned to the CPU pro- gram, which continues processing. 4.3 INTERFACE ELEMENTS The interface card provides a communication link between the computer and an external device. There are three basic elements on the interface card which either the computer or device can control inorder to effect the necessary communication. These elements are as follows: 4.3.1 CONTROL BIT This is a on-bit flip-flop register used by the computer to turn on the device channel. When set, the control bit generates a start 4-7 command to the device, telling it to begin one operation cycle (e.g., read or write one character or word). The interface cannot interrupt unless the control bit is set. The control bit is set by an STC (set control) instruction and cleared by a CLC (clear control) instruction, with a specific select code (e.g., STC 12 or CLC 12). The device cannot affect the control bit. 4.3.2 FLAG BIT This is a one-bit flip-flop register primarily used by the device to indicate, when set, that transmission between the device and the interface buffer has been completed. Computer instructions can also set the flag (STF), clear the flag (CLF), test if it is set (SFS), and test if it is clear (SFC). The device cannot clear the flag bit. If the corresponding control bit is set, priority is high, and the interrupt system is enabled, setting the flag bit will cause an inter- rupt to the location corresponding to the device's select code. 4.3.3 BUFFER This is a flip-flop register for intermediate storage of data. Typically the data capacity is 8 or 16 bits, but this is entirely dependent on the type of device. 4.4 I/O DATA TRANSFER The preceding paragraphs of this section have discussed the individ- ual features of the I/O system. The following paragraphs show how data is actually transferred under interrupt control. The se- quences are highly simplified in order to present an overall view, without the involvement of software operating systems and device drivers. For more detailed information refer to the documentation supplied with the appropriate software system or interface kit. 4.4.1 INPUT TRANSFER The upper part of figure 4.5 illustrates the sequence of operations for an input transfer. Note that some of the operations are under control of the computer program (programmer's responsibility) 4-8 and some of the operations are automatic. The sequence is as follows: The operation begins with a programmed instruction to set control and clear flag on the addressed interface card (1). In this example it is assumed that the interface card is installed in the slot for select code 12; thus the instruction is STC 12,C. Since the next few operations are under automatic control of the hardware, the computer program may continue executing other instructions. Setting the control bit causes the interface card to issue a start command (2) to the external device. The device then proceeds with its electromechanical process of reading a character. When it has done so, it sends a signal (done) back to the interface card, along with the data character (3). At the interface card the "done" signal sets the flag bit. The flag, in turn, generates an interrupt (4) -- provided the interrupt condi- tions previously mentioned are met. That is, the interrupt system must be on (STF 00 previously given), no higher priority interrupt may be requesting, and the control bit must be set (done in step 1). The interrupt causes the current computer program to be sus- pended, and control is transferred to a service subroutine (5). It is the programmer's responsibility to provide the linkage between the interrupt location (00012 in this case) and the service subroutine. Also, it is the programmer's responsibility to include in his service subroutine the instructions for processing of the data (loading into an accumulator, manipulating if necessary, and storing into memory). The subroutine may then issue further STC 12,C commands to transfer additional characters. One of the final instruction in the service routine must be a clear control (CLC 12 in this case). This step (6) allows lower priority devices to interrupt (equivalent to re-enabling a gate in figure 4.3) and restores the channel to its static "ready" condition -- control cleared and flag set. This condi- tion is initially established by the computer at turn-on, and it is the programmer's responsibility to return the channel to the same condition on the completion of each transfer. 4-9 At the end of the subroutine, control is returned to the interrupted program via previously established linkages. 4.4.2 OUTPUT TRANSFER The lower part of figure 4.5 illustrates the sequence of operations for an output transfer. Again note the distinction between pro- grammed and automatic operations. It is assumed that the data to be transferred has been loaded into A-register and is in a form suitable for output. The interface card is assumed to be installed in the slot for select code 13. The operation begins with a programmed instruction to transfer the data from the A-register to the interface buffer (1). The in- struction in this example is OTA 13. This is followed (2) by an instruction to set control and clear flag; i.e., STC 13,C. Since the next few operations are under automatic control of the hard- ware, the computer program may continue executing other instructions. Setting the control bit causes the interfac card to read out the buffer data to the device and to issue a start command (3). The de- vice proceeds to write the data, and when it has finished the de- vice sends a signal (done) back to the interface card (4). At the interface card the "done" signal sets the flag bit. The flag, in turn, generates an interrupt (5) -- providing the interrupt system is on, priority is high, and the control bit is still set (from step 2). The interrupt causes the current computer program to be suspended, and control is transferred to a service subroutine (6). It is the pro- grammer's responsibility to provide the linkage between the inter- rupt location (00013 in this case) and the service subroutine. The detailed contents of the subroutine is also the programmer's re- sponsibility, and will vary with the type of device. The subroutine may then output further data to the interface card and re-issue the STC 13,C command for additional character trans- fers. One of the final instructions in the service subroutine must be a clear control (CLC 13). This step (7) allows lower priority 4-10 Figure 4.5. Input/Output Transfers (Part 1) 4-11 Figure 4.5. Input/Output Transfers (Part 2) 4-12 devices to interrupt, and restores the channel to its static "ready" condition -- control cleared and flag set. At the end of the subrou- tine, control is returned to the interrupted program via previously established linkages. 4.4.3 NON-INTERRUPT TRANSFERS It is also possible to transfer data without using the interrupt sys- tem. This involves a "wait-for-flag" method, in which the computer commands the device to operate and then waits for the completion response. It is therefore assumed that computer time is relatively unimportant. The programming is very simple, consisting of only four words of in-line coding, as shown in table 4.1. Each of these routines will transfer one word or character of data. It is assumed that the interrupt system is turned off (STF 00 not previously given.) INPUT INSTRUCTIONS COMMENTS STC 12,C Start device SFS 12 Is input ready? JMP *-1 No, repeat previous instruction LIA 12 Yes, load input into A-register OUTPUT INSTRUCTIONS COMMENTS OTA 13 Output A-register to buffer STC 13,C Start device SFS 13 Has device accepted the data? JMP *-1 No, repeat previous instruction NOP Yes, proceed Table 4.1. Non-Interrupt Transfer Routines 4-13 INPUT. As before, an STC 12,C instruction begins the operation by commanding the device to read one word or character. The computer then goes into a waiting loop, repeatedly checking the status of the flag bit. If the flag is not set, the JMP *-1 instruction causes a jump back to the SFS instruction. (The *-1 operand is assembler notation for "this location minus one.") When the flag is set, the skip condition for SFS is met and the JMP instruction is skipped. The computer thus exits from the waiting loop, and the LIA 12 instruction loads the device's input data into the A- register. OUTPUT. The first step of output is to transfer the data to the interface buffer; the OTA 13 instruction does this. Then STC 13,C commands the device to operate and accept the data. The computer then goes into its waiting loop, the same as described in the pre- ceding paragraph. When the flag is received, indicating that the device has accepted the output data, the computer exits from the loop. (the final NOP is for illustration purposes only.) 4.5 DIRECT MEMORY ACCESS As indicated earlier in figure 4.1, the purpose of the direct memory access (DMA) option is to provide a direct data path, software assignable, between memory and a high-speed peripheral device. DMA accomplishes this purpose by stealing a memory cycle instead of interrupting to a service subroutine. The DMA option for the 2100A Computer is capable of stealing every consecutive memory cycle, and thus can transfer data at rates up to 1,020,400 words per second. There are two DMA channels, each of which may be separately assigned to operate with any I/O interface, including those in an HP 2155A I/O Extender. When both DMA channels are insimul- taneous operation, channel 1 has priority over channel 2. The combined maximum transfer rate for both channels operating to- gether is 1,020,400 words per second; the rate available to channel 2 is then the rate difference between 1,020,400 and channel 1's actual rate. When DMA is accessing memory, it has priority over CPU access of memory. Thus the rate available to the CPU when DMA is 4-14 operating is the difference between 1,020,400 words per second and the actual transfer rate of DMA channels 1 and 2 combined. DMA transfers are on a full-word basis; hardware packing and un- packing of characters is not provided. The word count register is a full 16 bits in length. DMA transfers are accomplished in blocks. The transfer is initiated by an initialization routine, and from then on operation is under automatic control of the hardware. The initialization routine tells DMA which direction to transfer the data (in or out), where in memory to put or take data, which I/O channel to use, and how much data to transfer. Completion of the block transfer is signalled by an interrupt to location 00006 (for channel 1) or location 00007 (for channel 2) if the interrupt system is enabled. It is also possible to check for completion by testing the status of the flag for select code 02 (for channel 1) or select code 03 (for channel 2). A block transfer can be aborted with an STF 06 or 07 instruction. 4.5.1 DMA OPERATION Figure 4.6 illustrates the sequence of operations for a DMA trans- fer. Comparison with conventional transfers (figure 4.5) shows that much more of the operation is automatic. Remember that the procedures in figure 4.5 must be repeated for each word or char- acter. In figure 4.6 the automatic DMA operations will transfer a block of data of any size, limited only by the availability of memory space. The sequence of events is as follows. (Input transfer is illustrated; the minor differences for output are explained in the text.) The initialization routine sets up the control registers on the DMA card (1) and issues the first start command (STC 12,C) directly to the interface card. (If the operation is output, the buffer is also loaded at this time.) The DMA option is then turned on and the computer program continues with other instructions. Setting control and clearing flag on the interface card (2) causes a start command (3) to the external device (with data if output). The device goes through its read or write cycle and returns a "done" signal (4), with data if input. The set flag, regardless of 4-15 Figure 4.6. DMA Transfers 4-16 priority, immediately requests DMA to steal a memory cycle (5) and a word is transferred into (or out of) memory (6). The pro- cess now repeats back to the beginning of this paragraph to trans- fer the next word. After the specified number of words has been transferred, the control bit is cleares (7). Then DMA generates an interrupt (8), and program control is forced to a completion routine (9), the contents of which is the programmer's responsibility. 4.5.2 DMA INITIALIZATION The information required to initialize DMA (direction, memory allocation, I/O channel assignment, and block length) are given by three control words. These three words must be addressed specifi- cally to the DMA card. Figure 4.7 shows the format of the three control words. CONTROL WORD 1 15 14 13 12 6 5 4 3 2 1 0 -------+-------+-------+--------/ /-------+----+----+----+----+----+---- | STC=1 | | CLC=1 | (Not Used) | Device Select code | | STC=0 | | CLC=0 | | | -------+-------+-------+-----/ /----------+----+----+----+----+----+---- CONTROL WORD 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 -------+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | IN=1 | Starting Memory Address | | OUT=0 | | -------+---+---+---+---+---+---+---+---+---+---+---+---+---+--- CONTROL WORD 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- | Word Count | | | ---+---+---+---+---+---+---+---+---+---+---+---+---+---+--- Figure 4.7. DMA Control Word Formats 4-17 Control Word 1 (CW1) identifies the I/O channel to be used, and provides for two options, selectable by the programmer as follows: Bit 15 1: Give STC (in addition to CLF) to I/O channel at end of each DMA cycle (except on last cycle, if input) 0: No STC Bit 13: 1: Give CLC to I/O channel at end of block transfer 0: No CLC Control Word 2 (CW2) gives the starting memory address for the block transfer and Bit 15 determines whether data is to go into memory (1) or out of memory (0). Control Word 3 (CW3) is the 2's complement of the number of words to be transferred into or out of memory; i.e., the length of block. This number can be from -1 to -32768, although it is limited in the practical case by available memory. Table 4.2 gives the basic program sequence for outputting the control words to DMA. As shown in this table, CLC 2 and STC 2 perform switching functions to prepare the logic for either CW2 or CW3. The device is assumed to be in I/O channel 10, and it is also assumed that its start command is STC 10B,C. The sample values of CW1, CW2, CW3 will read a block of 50 words and store these in locations 200 through 261 (octal). STC 6,C starts the DMA operation. A flag-status method for detecting end-of- transfer is used in this example; an interrupt to locaton 00006 could be substituted for this test. The program in table 4.2 could easily be changed to operate on channel 2 by changing select codes 2 to 3, and 6 to 7. One important difference should be noted when doing a DMA input operation from a disc or drum. Due to the asynchronous nature of disc or drum memories and the design of the interface, the order of starting must be reversed from the order given; i.e., start DMA first, then the disc. 4-18 Table 4.2. Program to Initialize DMA 4-19