MACHINE INSTRUCTIONS The HP Assembler langauge machine instruction codes take the form of three-letter mnemonics. Each source statement cor- responds to a machine operation in the object program pro- duced by the assembler. Notation used in representing source language instruction is as follows: label Optional statement label m Memory location -- an expression I Indirect addressing indicator sc Select code -- an expression C Clear interrupt flag indicator comments Optional comments [ ] Brackets defining a field or portion of a field that is optional { } Braces indicating that one of the set may be selected lit literal 3.1 MEMORY REFERENCE Memory Reference instructions perform arithmetic, logical and jump operations on the contents of the locations in core and the registers. An instruction may directly address the 2048 words of the current and base pages. If required, in- direct addressing may be utilized to refer to all 32,768 words of memory. Expressions in the operand field are evaluated modulo 2**10. If the program is to be assembled in relocatble form, the operand field may contain relocatable expressions or absolute expressions which are less than 100(8) in value. If the program is to be absolute, the operands may be any expressions con- sistent with the location of the program. Literals may not be used in an absolute program. Absolute programs must be complete entities; they may not refer to external subroutines or common storage. 3-1 JUMP AND INCREMENT-SKIP Jump and Increment-Skip instructions may alter the normal sequence of program execution. ------+-----+---------+-------- label JMP m[,I] comments Jump to m. Jump indirect inhibits interrupt until the transfer of control is complete. ------+-----+---------+-------- label JSB m[,I] comments Jump to subroutine. The address for label_1 is placed into the location represented by m and control transfers to m+1. On completion of the subroutine, control may be returned to the normal sequence by performing a JMP m,I. ------+-----+---------+-------- label ISZ m[,I] comments Increment, then skip if zero. ISZ adds 1 to the contents of m. If m then equals zero, the next instruction in memory is by- passed. ADD, LOAD, AND STORE Add, Load, and Store instructions transmit and alter the con- tents of memory and of the A- and B-Registers. A literal, indicated by "lit", may be either =D, =B, =A, or =I type. ------+-----+---------+-------- label ADA m[,I] comments lit Add the contents of m to A. ------+-----+---------+-------- label ADB m[,I] comments lit Add the contents of m to B. ------+-----+---------+-------- label LDA m[,I] comments lit Load A from m. ------+-----+---------+-------- label LDB m[,I] comments lit Load B from m. 3-2 ------+-----+---------+-------- label STA m[,I] comments Store contents of A in m. ------+-----+---------+-------- label STB m[,I] comments Store contents of B in m. In each instruction, the contents of the sending location is un- changed after execution. LOGICAL OPERATIONS The Logical operations allow bit manipulation and the com- parison of two computer words. ------+-----+---------+-------- label AND m[,I] comments The logical product of the contents of m and the contents of A are placed in A. ------+-----+---------+-------- label XOR m[,I] comments The modulo-two sum (exclusive "or") of the bits in m and the bits in A is placed in A. ------+-----+---------+-------- label IOR m[,I] comments The logical sum (inclusive "or") of the bits in m and the bits in A is placed in A. ------+-----+---------+-------- label CPA m[,I] comments Compare the contents of m with the contents of A. If they differ, skip the next instruction; otherwise, continue. ------+-----+---------+-------- label CPB m[,I] comments Compare the contents of m with the contents of B. If they differ, skip the next instruction; otherwise, continue. 3-3 3.2 REGISTER REFERENCE The Register Reference instructions include a Shift-Rorate group, an Alter-Skip group, and NOP (no-operation). With the exception of NOP, they have the capability of causing several actions to take place during one memory cycle. Mul- tiple operations within a statement are separated by a comma. SHIFT-ROTATE GROUP This group contains 19 basic instructions that can be combined to produce more then 500 different single cycle operations. CLE Clear E to zero ALS Shift A left one bit, zero to least significant bit. Sign unaltered BLS Shift B left one bit, zero to least significant bit. Sign unaltered ARS Shift A right one bit, extend sign; sign unaltered. BRS Shift B right one bit, extend sign; sign unaltered. RAL Rotate A left one bit RBL Rotate B left one bit RAR Rotate A right one bit RBR Rotate B right one bit ALR Shift A left one bit, clear sign, zero to least significant bit BLR Shift B left one bit, clear sign, zero to least significant bit ERA Rotate E and A right one bit ERB Rotate E and B right one bit ELA Rotate E and A left one bit ELB Rotate E and B left one bit ALF Rotate A left four bits BLF Rotate B left four bits SLA Skip next instruction if least significant bit in A is zero SLB Skip next instruction if least significant bit in B is zero 3-4 These instructions may be combined as follows: ------+-----------------------+------- ALS ALS ARS ARS RAL RAL label RAR , CLE , SLA , RAR comments ALF ALF ERA ERA ELA ELA ------+-----------------------+------- BLS BLS BRS BRS RBL RBL label RBR , CLE , SLB , RBR comments BLF BLF ERB ERB ELB ELB CLE, SLA or SLB appearing alone or in any valid combination with each other are assumed to be a Shift-Rotate machine instruction. The Shift-Rotate instructions must be given in the order shown. At least one and up to four are included in cone state- ment. Instructions referring to the A-register may not be combined in the same statement with those referring to the B-register. NO-OPERATION INSTRUCTION When a no-operation is encountered in a program, no action takes place; the computer goes on to the next instruction. A full memory cycle is used in executing a no-operation instruc- tion. ------+-----+---------+-------- label NOP comments A subroutine to be entered by a JSB instruction should have a 3-5 NOP as the first statement. The return address can be stored in the location occupied by the NOP during executionof the program. A NOP statement causes the Assembler to generate a word of zeros. ALTER-SKIP GROUP The Alter-Skip group contains 19 basic instructions that can be combined to produce more than 700 different single cycle operations. CLA Clear the A-Register CLB Clear the B-Register CMA Complement the A-Register CMB Complement the B-Register CCA Clear, then complement the A-Register (set to ones) CCB Clear, then complement the B-Register (set to ones) CLE Clear the E-Register CME Complement the E-Register CCE Clear, then complement the E-REgister SEZ Skip next instruction if E is zero SSA Skip if sign of A is positive (0) SSB Skip if sign of B is positive (0) INA Increment A by one. INB Increment B by one. SZA Skip if contents of A equals zero SZB Skip if contents of B equals zero SLA Skip if least significant bit of A is zero SLB Skip if least significant bit of B is zero RSS Reverse the sense of the skip instructions. If no skip instructions precede in the statement, skip the next instruction. 3-6 These instructions may be combined as follows: ------+-----------------------------------------------+------- CLA CLE label CMA , SEZ , CME , SSA , SLA , INA , SZA , RSS comments CCA CCE ------+-----------------------------------------------+------- CLB CLE label CMB , SEZ , CME , SSB , SLB , INB , SZB , RSS comments CCB CCE The Alter-Skip instructions must be given in the order shown. At least one and up to eight are included in one statement. In- structions referring to the A-register may not be combined in the same statement with those referring to the B-register. When two or more skip functions are combined in a single operation, a skip occurs if any one of the conditions exists. If a word with RSS also includes both SSA and SLA (or SSB and SLB) a skip occurs only when sign and least significant bit are both set (1). 3.3 INPUT/OUTPUT, OVERFLOW, AND HALT The input/output instructions allow the user to transfer data to and from an external device via a buffer, to enable or dis- able external interrupt, or to check the status of I/O devices and operations. A subset of these instructions permits check- ing for an arithmetic overflow condition. Input/Output instructions require the designation of a select code, sc, which indicates one of 64 input/output channels or functions. Each channel consists of a connect/disconnect con- trol bit, a flag bit, and a buffer of up to 16 bits. The setting of the control bits indicates that a device associated with the channel is operable. The flag bit is set automatically when transission between the device and the buffer is completed. Instructions are also available to test or clear the flag bit for the particular channel. If the interrupt system is enabled, setting of the flag causes program interrupt to occur; control transfers to the interrupt location related to the channel. 3-7 Expressions used to represent select codes (channel numbers) must have a value of less than 2**6. The value specifies the de- vice or operation referenced. Instructions which transfer data between the A or B register and a buffer, access the Switch register when sc = 1. The character C appended to such an instruction clears the overflow bit after the transfer from the Switch register is complete. INPUT/OUTPUT Prior to any input/output data transmission, the control bit is set. The instruction which enables the device may also trans- fer data between the device and the buffer. ------+-----+---------+-------- label STC sc [,C] comments Set I/O control bit for channel specified by sc. STC transfers or enables transfer of an element of data from an input device to the buffer or to an output device from the buffer. The exact functon of STC depends on the device; for the 2752A Teleprinter, an STC enables transfer of a series of bits. If sc = 1, this statement is treated as NOP. The C option clears the flag bit for the channel. ------+-----+---------+-------- label CLC sc [,C] comments Clear I/O control bit for channel specified by sc. When the control bit is cleared, interrupt on the channel is disabled, although the flag may still be set by the device. If sc = 0, control bits for all channels are cleared to zero; all devices are disconnected. If sc - 1 this statement is treated as NOP. ------+-----+---------+-------- label LIA sc [,C] comments Load into A the contents of the I/O buffer indicated by sc. ------+-----+---------+-------- label LIB sc [,C] comments Load into B the contents of the I/O buffer indicated by sc. ------+-----+---------+-------- label LIA sc [,C] comments Merge (inclusive "or") the contents of the I/O buffer indicated by sc into A. 3-8 ------+-----+---------+-------- label MIA sc [,C] comments Merge (inclusive "or") the contents of the I/O buffer indicated by sc into B. ------+-----+---------+-------- label OTA sc [,C] comments Output the contents of A to the I/O buffer indicated by sc. ------+-----+---------+-------- label OTB sc [,C] comments Output the contents of B to the I/O buffer indicated by sc. ------+-----+---------+-------- label STF sc comments Sets the flag bit of the channel indicated by sc. If sc = 0, STF enables the interrupt system. A sc code of 1 causes the over- flow bit to be set. ------+-----+---------+-------- label CLF sc comments Clear the flag bit to zero for the channel indicated by sc. If sc = 0, CLF disables the interrupt system, If sc = 1, the overflow bit is cleared to zero. ------+-----+---------+-------- label SFC sc comments Skip the next instruction if the flag bit for channel sc is clear. If sc = 1, the overflow is tested. ------+-----+---------+-------- label SFS sc comments Skip the next instruction if the flag bit for channel sc is set. If sc = 1, the overflow is tested. OVERFLOW In addition to the use of a select code of 1, the overflow bit may be accessed by the following instructions: 3-9 ------+-----+---------+-------- label CLO comments Clear the overflow bit. ------+-----+---------+-------- label STO comments Set the overflow bit. ------+-----+---------+-------- label SOC [C] comments Skip the next instruction if the overflow bit is clear. The C option clears the bit after the test is performed. ------+-----+---------+-------- label SOS [C] comments Skip the next instruction if the overflow bit is set. The C option clears the bit after the test is performed. The C option is identified by the sequence 'space C space' follow- ing either 'SOC' or 'SOS'. Anything else is treated as a comment. HALT ------+-----+---------+-------- label HLT [sc[,C]] comments [C] Halt the computer. The machine instruction word is displayed in the T-Register. If the C option is used, the flag bit associ- ated with channel sc is cleared. If neither the select code nor the C option is used, the com- ments portion must be omitted. 3-10 3.4 EXTENDED ARITHMETIC INSTRUCTIONS Ten instructions are used with the extended arithmetic version of the Assembler or Extended Assembler to increase the computer's overall efficiency. They provide for integer multiply and divide and for loading and storing double-length words to and from the accumulators. ------+-----+---------+-------- label MPY m[,I] comments lit The MPY instruction multiplies the contents of the A-Register by the contents of M. The product is stored in registers B and A. B contains the sign of the product and the 15 most significant bits; A contains the least significant bits. ------+-----+---------+-------- label DIV m[,I] comments lit The DIV instruction divides the contents of registers B and A by the contents of m. The quotient is stored in A and the remainder in B. Initially B contains the sign and the 15 most significant bits of the dividend; A contains the least significant bits. ------+-----+---------+-------- label DLD m[,I] comments lit The DLD instruction loads the contents of locations m and m + 1 into registers A and B, respectively. ------+-----+---------+-------- label DST m[,I] comments The DST instruction stores the contents of registers A and B in locations m and m + 1, respectively. MPY, DIV, DLD, DST results in two machine words: a word for the instruction code and one for the operand. 3-11 The above four instructions are available without the extended arithmetic instructions as software subroutines. [1] However, by using the extended arithmetic group, they require less core storage and can be executed in less time. The following shift-rotate instructions provide the capability to shift or rotate the B- and A- Registers n number of bit positions, where 1 <= n <= 16. ------+-----+---------+-------- label ASR n comments The ASR instruction arithmetically shifts the B- and A- Registers right n bits. The sign bit (bit 15 of B) is extended. ------+-----+---------+-------- label ASL n comments The ASL instruction arithmetically shifts the B- and A- Registers left n bits. Zeroes are placed in the least significant bits. The sign bit (bit 15 of B) is unaltered. The overflow bit is set if bit 14 differs from bit 15 before each shift, otherwise, exit with Overflow bit cleared. ------+-----+---------+-------- label RRR n comments The RRR instruction rotates the B- and A-Registers right n bits. ------+-----+---------+-------- label RRL n comments The RRL instruction rotates the B- and A-Registers left n bits. ------+-----+---------+-------- label LSR n comments The LSR instruction logically shifts the B- and A-Registers right n bits. Zeroes are placed in the most significant bits. ------+-----+---------+-------- label LSL n comments The LSL instruction logically shifts the B- and A-Registers left n bits. Place zeroes in the least significant bits. --------------------- [1] See ARITHMETIC SUBROUTINE CALLS, Section 4.7. 3-12 3.5 FLOATING-POINT INSTRUCTIONS Floating-point instructions provide a means of performing calcu- lations on floating-point values. Computers with the hardware floating-point option should use assemblers and libraries with floating-point capabilities. The floating-point assembler gener- ates calls to the appropriate hardware function instead of the library subroutines. If the computer does not have the hardware floating-point option, then non-floating-point assemblers and libraries should be used. ------+-----+---------+-------- label FAD m[,I] comments lit FAD performs an addition between a floating-point number stored in the A- and B-Registers and a floating-point number stored in memory locations m and m + 1. The result is returned in the A- and B-Registers. ------+-----+---------+-------- label FSB m[,I] comments lit The FSB instruction subtracts a floating-point value in memory locations m and m + 1 from a floating-point value in the A- and B-Registers. The result is returned in the A- and B-Registers. ------+-----+---------+-------- label FMP m[,I] comments lit The FMP instruction multiplies a floating-point value in memory locations m and m + 1 with a floating-point value in the A- and B-Registers. The result is returned in the A- and B-Registers. ------+-----+---------+-------- label FDV m[,I] comments lit The FDV instruction divides a floating-point value in memory locations m and m + 1 into a floating-point value in the A- and B-Registers. The result is returned in the A- and B-Registers. 3-13 ------+-----+---------+-------- label FIX comments The FIX instruction converts a floating-point number contained in the A- and B-Registers to a fixed point number. The result is returned in the A-Register. The contents of the B-Register are meaningless. ------+-----+---------+-------- label FLT comments The FLT instruction converts a fixed-point number contained in the A-Registers to a floating-point value. The result is returned in the A- and B-Registers. 3-14